The present invention relates to data caching by computers. More particularly, the present invention relates to a computer system and method for controlling the mode of operation of a data cache to ensure data integrity.
Advanced computer systems usually include large data caches in addition to instruction caches. Data caches can dramatically improve system performance by providing cached data to execution units with very low latency and by increasing the availability of the system bus for use by external devices. Such external devices may include direct memory access (DMA) agents that provide direct access to data stored in the system's memory. Examples of DMA agents include various storage devices, input/output (I/O) ports, communication devices, as well as other types of separate processors in a shared-bus system. DMA cycles performed by DMA agents include read cycles, wherein data is read directly from the memory, and write cycles, wherein data is written directly to the memory.
Systems which use data caches and support DMA cycles need some mechanism to ensure integrity between cached data and data stored in the memory. Most conventional solutions to this problem involve data snooping, a well know technique to maintain data integrity by monitoring DMA cycles and performing cache maintenance operations in response to LAW specific DMA operations. For example, in response to a DMA to a particular line of memory, matching cache lines can be invalidated during the DMA access or the memory portion can be inhibited to allow the processor to respond to the access as a slave. By intervening in the access, the processor can update its internal cache for a DMA write cycle or supply cache data to the DMA agent for a DMA read cycle.
Data integrity may also be supported by switching the mode of the cache between writethrough, copyback, and cache-inhibited (noncacheable) modes for specific memory segments. In writethrough mode, writes by the processor to locations in the cache change the target location of the main memory as well as the cache memory. In copyback mode, writes by the processor to locations in the cache only change the cache memory, not the main memory. In cache-inhibited mode, the cache is deactivated so that no cache reads or writes occur. Typically, the modes of cache operation associated with specific memory segments are stored as tags within a memory management unit (MMU) associated with the processor.
For example, using data snooping, a memory segment shared by the processor and DMA agents can be designated in copyback mode, allowing both the processor and the DMA agents to cache the data. Because all cache writes will be written to the target address of the memory, the snooping mechanism will ensure the integrity of the other cached copies of the data.
The MC68040 microprocessor manufactured by Motorola Inc. of Phoenix, Ariz. supports snooping and cache mode switching. That microprocessor's cache coherency mechanism as well as its data cache operation modes and the storage tags are further described in Section 7 of the MC68040 32-Bit Microprocessor User's Manual (1989), which is incorporated herein by reference.
While some systems may employ data snooping techniques to ensure data integrity, others systems include DMA agents which cannot efficiently support or are incompatible with the data snooping mechanism of other components. For example, certain types of DRAM controllers do not support snooping for a MC68040 microprocessor. Moreover, without the use of snooping, cache mode switching alone cannot ensure data integrity, except in those systems where the memory management system knows the locations accessible to every DMA agent prior to run time.
Thus, systems incapable of data snooping, and for which all memory locations accessible to DMA agents are not known in advance, cannot use data caches. As a result, the system's performance suffers. Accordingly, there remains a need for a computer system and method for controlling the mode of operation of a data cache to ensure data integrity which does not rely on data snooping and does not require prior knowledge of memory locations accessible by the DMA agents.